High speed computing normally requires many-fold repetitive arithmetic operations (addition, subtraction, multiplication, division, exponentiation, etc.). An increase in efficiency of one or more of such operations translates directly into proportionate time savings in computer operation. In floating point operations, whereby any numerical operand x (.noteq. 0) is represented by a unique ordered pair of numbers (e, f) such that e is an integer and f satisfies 1 .ltoreq. .vertline.f.vertline. &lt; 2 so that x=2.sup.e f, paradoxically, the addition and subtraction operations are more cumbersome than the operations of multiplication, division and exponentiation. Thus, efficiency improvements in floating point addition and subtraction are of special interest.
Bohm, in U.S. Pat. No. 3,315,069, discloses and claims a computer that is constructed to always form the quantity F(a, b, c, d)=(a.+-.b).times.c.div.d in response to any binary arithmetic input (a, b) or (a, c) or (a, d) or (b, c) or (b, d) or (c, d); with the other two arithmetic inputs being chosen to produce the particular arithmetic result desired. For example, if the difference a-b is desired, the function F and its four inputs become F(a, -b, 1, 1)=(a-b).times.1=a-b; and if the quotient a.div.d (d.noteq.0) is called for, the function F and its inputs becomes F(a, 0, 1, d)=a/d. Groups of four registers, one containing each of the inputs a, (.+-.)b, c and d, are logically connected so that the result F(a, b, c, d)=(a.+-.b).times.c/d is always produced. The inventor notes that time for addition or subtraction in this scheme is substantially longer than addition or subtraction in a conventional approach. And use of floating point numbers would pose further problems and require additional computer time.
Kindell et al disclose and claim computer apparatus for consistently "rounding off" positive and negative numbers in 2's complement representations of floating point numbers, in U.S. Pat. No. 3,699,326. A rounding constant, different for positive and for negative numbers, is added to such numbers for purposes of storage or comparison. The logic used causes consistent round up (round down) to an n-bit number if the actual, untruncated number minus the n-bit truncated number lies closest to or equidistant between the "upper" ("lower") of two adjacent values of the number truncated at the n.sup.th bit. No means of forming sums or differences of two floating point numbers is discussed.
Method and apparatus for approximately simultaneous computer computation and processing of coefficients for two Fast Fourier Transform algorithms is disclosed and claimed in U.S. Pat. No. 3,721,812, issued to Schmidt. In one embodiment, the Schmidt invention interlaces two serial streams of appropriate data in a single serial access memory so that two Fast Fourier Transforms may be calculated substantially simultaneously, thus reducing the time normally required for computation of the FFT by approximately 50 percent. However, the invention does not concern simultaneous performance of additions and subtractions of floating point representations of numbers.